D2-4 Prototype sources for Heterogeneous Implementation of Initial Generic Patterns
Deliverable D2.1 introduced the initial set of generic patterns for the Para- Phrase project. The patterns in the initial set can be used to implement parallel applications according to the structured parallel programming methodology that is typical of the design patterns and/or algorithmic skeletons approaches. Deliverable D2.2 described the implementation of the initial set of patterns targeting homogeneous multicore architectures. This deliverable describes the implementation of the initial generic pattern set on heterogeneous architectures, that is on architectures containing both multicore CPUs and General Purpose GPUs (GPGPUs). We focus on the implementation of the data parallel patterns from the initial pat- tern set (map and reduce), since the task parallel patterns that were described there (pipeline and farm) do not fit the data parallel execution model that is typical of GPGPUs.
This deliverable describes two different implementations of the initial data parallel patterns. The first implementation provides data parallel skeletons implementing the initial data parallel pattern set on GPUs. These are provided as suitable FastFlow abstractions. The second implementation provides similar skeletons as Erlang functions that can be seamlessly used in any Erlang program. In both cases, the GPU implementation of the data parallel skeletons runs on top of OpenCL, although some CUDA support is also provided.
This is the file with the implementation of data parallel skeletons on GPUs (through SKEPU) provided as regular Erlang functions.
198 kB (202906 bytes)
This is the file with the version of FastFlow extended to implement the initial generic data parallel patterns on GPUs
18089 kB (18523664 bytes)
This is a Virtual Machine hosting both the FastFlow version implementing the initial generic data parallel patterns on GPUs and the Erlang GPU implementation of the same patterns.
1663270 kB (1703188480 bytes)
941 kB (963851 bytes)